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Bit
Name
Reset
Access
Description
Set when data is incoming while the receive shift register is full. The data previously in the shift register is lost.
3
RXFULL
0
R
RX Buffer Full Interrupt Flag
Set when the receive buffer becomes full.
2
RXDATAV
0
R
RX Data Valid Interrupt Flag
Set when data becomes available in the receive buffer.
1
TXBL
1
R
TX Buffer Level Interrupt Flag
Set when buffer becomes empty if TXBIL is set, or when buffer goes from full to half-full if TXBIL is cleared
0
TXC
0
R
TX Complete Interrupt Flag
This interrupt is used after a transmission when both the TX buffer and shift register are empty.
16.5.18 USARTn_IFS - Interrupt Flag Set Register
Offset
0x044
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:13
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
12
CCF
0
W1
Set Collision Check Fail Interrupt Flag
Write to 1 to set the CCF interrupt flag.
11
SSM
0
W1
Set Slave-Select in Master mode Interrupt Flag
Write to 1 to set the SSM interrupt flag.
10
MPAF
0
W1
Set Multi-Processor Address Frame Interrupt Flag
Write to 1 to set the MPAF interrupt flag.
9
FERR
0
W1
Set Framing Error Interrupt Flag
Write to 1 to set the FERR interrupt flag.
8
PERR
0
W1
Set Parity Error Interrupt Flag
Write to 1 to set the PERR interrupt flag.
7
TXUF
0
W1
Set TX Underflow Interrupt Flag
Write to 1 to set the TXUF interrupt flag.
6
TXOF
0
W1
Set TX Overflow Interrupt Flag
Write to 1 to set the TXOF interrupt flag.
5
RXUF
0
W1
Set RX Underflow Interrupt Flag
Write to 1 to set the RXUF interrupt flag.
4
RXOF
0
W1
Set RX Overflow Interrupt Flag
Write to 1 to set the RXOF interrupt flag.
3
RXFULL
0
W1
Set RX Buffer Full Interrupt Flag
Write to 1 to set the RXFULL interrupt flag.
2:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0
TXC
0
W1
Set TX Complete Interrupt Flag
Write to 1 to set the TXC interrupt flag.
2011-04-12 - d0001_Rev1.10
212
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